`timescale 1ms/1ms
module elock;
reg clk, rst;
 wire [7:0] qLEDaddr;
 wire [5:0] CS;
initial
begin
 clk  = 1'b0;
 rst = 1'b1;
 #100 rst = 1'b0;
 key_s=1'b0;
 key_m=1'b0;
 key_h=1'b0;
end
always #1  clk = ~clk;
HMS_eclock m1(
	 .key_s(key_s),
	 .key_m(key_m),
	 .key_h(key_h),
    .clk_12M(clk),
    .rst(rst),
    .qLEDaddr(qLEDaddr),
    .CS2(CS));
endmodule
